In order to accommodate increased integration densities, ferroelectric materials such as PZT (PbZrTiO.sub.3) and BST (BaSrTiO.sub.3) have been used to provide dielectric layers for capacitors. In particular, these dielectric materials have been used in dynamic random access memory (DRAM) devices and in ferroelectric random access memory (FRAM) devices. When using ferroelectric materials to provide capacitor dielectric layers, the lower capacitor electrodes have typically been formed from platinum and related elements and oxides thereof. In general, an insulating layer is formed on a substrate, and a contact hole is formed in the insulating layer exposing a portion of the substrate. A contact plug is then formed in the contact hole, and the lower capacitor electrode is formed on the contact plug and on the insulating layer. In addition, a barrier layer may be formed between the contact plug and the lower electrode of the capacitor.
FIG. 1 is a cross-sectional view illustrating a ferroelectric capacitor for a semiconductor device according to the prior art. As shown, an insulating layer 3 having a contact hole therein is formed on the semiconductor substrate 1. A polysilicon contact plug 5 is formed in the contact hole, and a TiN barrier layer 7 is formed on the insulating layer 3 and on the contact plug 5. A diffusion barrier layer 9 reduces the diffusion of oxygen into the barrier layer 7. This diffusion barrier layer 9 can be a layer of Ir or IrO.sub.2. A lower capacitor electrode 11 is formed on the diffusion barrier layer 9, and this lower capacitor electrode can be a layer of platinum. A ferroelectric layer 13 and an upper capacitor electrode 15 are then formed on the lower electrode 11. Accordingly, the lower capacitor electrode 11, the ferroelectric layer 13, and the upper capacitor electrode define a ferroelectric capacitor.
In a semiconductor device having a relatively low integration density, lateral exposure of the barrier layer 7 may be insignificant even when the pattern is misaligned because the lower electrode is relatively large in size. As integration densities increase, however, the relative size of the lower capacitor electrode is reduced. Accordingly, significant portions of the barrier layer 7 may be oxidized during high temperature thermal treatments used during and after the deposition of the ferroelectric layer because the lateral surfaces of the lower electrode and the barrier layer are exposed. Furthermore, the contact plug 5 may also be oxidized. If the barrier layer 7 and/or the contact plug 5 are oxidized, a contact resistance between the contact plug 5 and the lower capacitor electrode 11 may increase thereby reducing the performance of the capacitor.
Methods have thus been proposed to form spacers on lateral surfaces of the barrier layer to reduce exposure thereof. The use of spacers, however, may increase the complexity of fabrication, and misalignment margins between the contact hole and the lower capacitor electrode may be insufficient. Accordingly, if misalignment occurs between the lower capacitor electrode and the contact hole, the barrier layer may be exposed during later fabrication steps.
FIG. 2 is a cross-sectional view illustrating misalignment between a contact hole and a lower electrode during the fabrication of a conventional ferroelectric capacitor. As shown, an insulating layer 23 has a contact hole therein exposing a portion of the semiconductor substrate 21. A polysilicon contact plug 25 is formed in the contact hole, and a TiN barrier layer 27 is formed on the contact plug 25. In addition, a lower capacitor electrode 29 is formed on the barrier layer 27. As shown, misalignment may occur between the lower capacitor electrode 29 and the contact hole thereby exposing a portion of the barrier layer 27 as indicated by reference numeral 200.
If the barrier layer is exposed, the barrier layer may be oxidized during the subsequent step of depositing a ferroelectric layer. A contact resistance between the contact plug and the lower capacitor electrode may thus be undesirably increased thereby reducing the performance of the capacitor. As discussed above, the oxidation of the barrier layer may result from the exposure thereof when forming the ferroelectric layer. In a relatively highly integrated device, this exposure may occur as a result of misalignment.
Accordingly, there continues to exist a need in the art for improved ferroelectric capacitor structures and related methods.